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A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.

, , , , , and . ISED, page 100-105. IEEE Computer Society, (2011)

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Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs., , , , , , , and . VLSI Design, page 280-285. IEEE Computer Society, (2012)A Prefix Based Reconfigurable Adder., , , , , and . ISVLSI, page 349-350. IEEE Computer Society, (2011)A Novel, Variable Resolution Flash ADC with Sub Flash Architecture., , , and . ISVLSI, page 434-435. IEEE Computer Society, (2010)Comparison of Voltage Charging Techniques to Increase the Life of Lead Acid Batteries., , , and . iSES, page 279-284. IEEE, (2018)A low power, variable resolution two-step flash ADC., , , , and . ACM Great Lakes Symposium on VLSI, page 39-44. ACM, (2010)A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block., , , , , and . ISED, page 100-105. IEEE Computer Society, (2011)Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders., , , , , and . ISVLSI, page 225-230. IEEE Computer Society, (2012)A Modified Twin Precision Multiplier with 2D Bypassing Technique., , , , and . ISED, page 102-106. IEEE, (2012)Low power, variable resolution pipelined analog to Digital converter with sub flash architecture., , , , and . APCCAS, page 204-207. IEEE, (2010)Design of Prefix-Based Optimal Reversible Comparator., , , , , and . ISVLSI, page 201-206. IEEE Computer Society, (2012)