Author of the publication

Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis.

, , , , and . ASPLOS, page 555-568. ACM, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

SecDCP: secure dynamic cache partitioning for efficient timing channel protection., , , , and . DAC, page 74:1-74:6. ACM, (2016)Policy Transparency: Authorization Logic Meets General Transparency to Prove Software Supply Chain Integrity., , , and . SCORED@CCS, page 3-13. ACM, (2022)Timing channel protection for a shared memory controller., , and . HPCA, page 225-236. IEEE Computer Society, (2014)Low-overhead and high coverage run-time race detection through selective meta-data management., , , and . HPCA, page 96-107. IEEE Computer Society, (2014)Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller., , , , and . HPCA, page 382-393. IEEE Computer Society, (2016)Detecting Hardware Trojans using On-chip Sensors in an ASIC Design., , , and . J. Electron. Test., 31 (1): 11-26 (2015)Komodo: Using verification to disentangle secure-enclave hardware from software., , , and . SOSP, page 287-305. ACM, (2017)Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis., , , , and . ASPLOS, page 555-568. ACM, (2017)Secure Autonomous Cyber-Physical Systems Through Verifiable Information Flow Control., , , , , , , and . CPS-SPC@CCS, page 48-59. ACM, (2018)HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security., , , and . CCS, page 1583-1600. ACM, (2018)