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Disambiguation of "Chang, Mau-Chung Frank"

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A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS.

, , , , and . CICC, page 1-4. IEEE, (2011)

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Chung-kong Chang

Wei-chung Chang

Ya-chung Chang

Chuen Chung Chang

Frank Mau

 

Other publications of authors with the same name

A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization., , , , , and . A-SSCC, page 1-3. IEEE, (2023)A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration., , , , , , , and . CICC, page 1-4. IEEE, (2012)2.1 A highly linear inductorless wideband receiver with phase- and thermal-noise cancellation., , , , and . ISSCC, page 1-3. IEEE, (2015)RF-Interconnect for Future Network-On-Chip., , , , and . Low Power Networks-on-Chip, Springer, (2011)Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers., , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)CMOS receivers for active and passive mm-wave imaging., , and . IEEE Communications Magazine, 49 (10): 190-198 (2011)6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX., , , , , , , , , and 1 other author(s). ESSCIRC, page 258-261. IEEE, (2010)An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch., , , , , , , and . ESSCIRC, page 83-86. IEEE, (2019)A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input., , , , and . ISCAS, page 2047-2051. IEEE, (2022)