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Disambiguation of "Sashikánth, Milagros"

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A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.

, , , and . ASP-DAC, page 791-794. ACM Press, (2005)

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Maria Milagros Becker

Milagros Mendoza-Gärtner

Maria los Milagros Bassani Molinas

 

Other publications of authors with the same name

A function generator-based reconfigurable system., , , and . ASP-DAC, page 905-909. ACM Press, (2005)Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs., , , , and . VLSI Design, page 736-741. IEEE Computer Society, (2005)Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs., , , , and . IPDPS, IEEE Computer Society, (2005)Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)., , , , and . FPGA, page 265. ACM, (2005)An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs., , , and . VLSI Design, page 507-510. IEEE Computer Society, (2006)A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs., , , , and . FPT, page 121-128. IEEE, (2004)Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs., , , , and . ASP-DAC, page 1200-1203. ACM Press, (2005)A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs., , , and . ASP-DAC, page 791-794. ACM Press, (2005)