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Disambiguation of "Joshi, Ajay"

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Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5183-5196 (2020)

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Ajay Chavan

Godwin Olu Ajayi

Jidnyasa Joshi

Ajay Wakhloo

Ajay Moza

 

Other publications of authors with the same name

Sub-threshold logic circuit design using feedback equalization., and . DATE, page 1-6. European Design and Automation Association, (2014)Network-on-Chip Microarchitecture-based Covert Channel in GPUs., , , , , , , and . MICRO, page 565-577. ACM, (2021)SealPK: Sealable Protection Keys for RISC-V., , , and . DATE, page 1278-1281. IEEE, (2021)FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption., , , , , , , and . HPCA, page 882-895. IEEE, (2023)MGPU-TSM: A Multi-GPU System with Truly Shared Memory., , , , , , , , and . CoRR, (2020)Leveraging Residue Number System for Designing High-Precision Analog Deep Neural Network Accelerators., , , , and . CoRR, (2023)FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption., , , , , , , and . CoRR, (2022)Efficient Sealable Protection Keys for RISC-V., , , and . CoRR, (2020)UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs., , , , , , , , and . ACM Trans. Archit. Code Optim., 13 (4): 35:1-35:25 (2016)MGSim + MGMark: A Framework for Multi-GPU System Research., , , , , , , , , and 3 other author(s). CoRR, (2018)