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Disambiguation of "Narayan, Aditya"

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Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5183-5196 (2020)

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Aditya Narayan Tripathi

Aditya Aryasomayajula

Aditya Devarakonda

Aditya Kumar

Aditya Malik

 

Other publications of authors with the same name

Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5183-5196 (2020)MOCA: Memory Object Classification and Allocation in Heterogeneous Memory Systems., , , , and . IPDPS, page 326-335. IEEE Computer Society, (2018)Bandwidth Allocation in Silicon-Photonic Networks Using Application Instrumentation., , and . HPEC, page 1-2. IEEE, (2020)WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs., , , , and . DATE, page 516-521. IEEE, (2019)Body Composition in Anti-Obesity Medication Trials—Beyond Scales, , and . 184 (4): 341 (2024)PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2156-2169 (2021)Architecting Optically-Controlled Phase Change Memory., , , , and . CoRR, (2021)Energy-efficient architectures for chip-scale networks and memory systems using silicon-photonics technology. Boston University, USA, (2021)Architecting Optically Controlled Phase Change Memory., , , , and . ACM Trans. Archit. Code Optim., 19 (4): 48:1-48:26 (2022)System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications., , , , and . DATE, page 1444-1449. IEEE, (2020)