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A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators., , , , , и . APCCAS, стр. 1011-1014. IEEE, (2010)A process- and temperature- insensitive current-controlled delay generator for sampled-data systems., , , , , и . APCCAS, стр. 1192-1195. IEEE, (2008)An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications., , , , , , и . ICECS, стр. 878-881. IEEE, (2010)A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators., , , , , и . ICECS, стр. 547-550. IEEE, (2010)Hybrid loopfilter sigma-delta modulator with NTF zero compensation., , , и . ISOCC, стр. 76-79. IEEE, (2011)A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction., , , , , и . ESSCIRC, стр. 169-172. IEEE, (2016)A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS., , , , , , , и . ISCAS, стр. 2239-2242. IEEE, (2013)A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer., , , , , и . ISCAS, стр. 65-68. IEEE, (2012)A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure., , , , и . VLSIC, стр. 86-87. IEEE, (2012)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC., , , , , , и . IEEE J. Solid State Circuits, 47 (11): 2763-2772 (2012)