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Disambiguation of "Han, Jin-Man"

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Session 7 overview: Nonvolatile memory solutions.

, and . ISSCC, page 128-129. IEEE, (2016)

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Man-Jung Han

Jong-Man Han

Kyung-Man Han

Man Jin Choi

Sang-jin Han

 

Other publications of authors with the same name

Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH., , , , , , , , , and . VLSIC, page 136-137. IEEE, (2012)A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology., , , , , , , , , and 27 other author(s). ISSCC, page 430-432. IEEE, (2012)A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory., , , , , , , , , and 7 other author(s). VLSIC, page 132-133. IEEE, (2012)A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 31 (11): 1635-1644 (1996)Session 12 overview: Non-volatile memory solutions., and . ISSCC, page 208-209. IEEE, (2013)A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 47 (4): 981-989 (2012)19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming., , , , , , , , , and 35 other author(s). ISSCC, page 334-335. IEEE, (2014)Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 204-213 (2015)Session 7 overview: Nonvolatile memory solutions., and . ISSCC, page 128-129. IEEE, (2016)F2: VLSI power-management techniques: Principles and applications., , , , , and . ISSCC, page 502-503. IEEE, (2013)