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Disambiguation of "Bowman, Keith A."

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Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).

, , , and . SLIP, page 147-148. ACM, (2000)

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Brady Bowman

Benjamin Bowman

Howard Bowman

Jon Franz Keith

Caren Christine Keith

 

Other publications of authors with the same name

A physical alpha-power law MOSFET model., , , , and . IEEE J. Solid State Circuits, 34 (10): 1410-1414 (1999)A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1173-1184 (2019)Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)., , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 899-912 (2001)Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration., , and . IEEE J. Solid State Circuits, 37 (2): 183-190 (2002)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors., , , , , , , , , and 4 other author(s). ISSCC, page 316-318. IEEE, (2019)Welcome to ISQED 2013., , , , , , , and . ISQED, IEEE, (2013)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , and . VLSI Circuits, page 65-66. IEEE, (2018)Resilient microprocessor design for high performance & energy efficiency., , , , , , , , , and 1 other author(s). ISLPED, page 355-356. ACM, (2010)