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SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement.

, , and . Asian Test Symposium, page 193-199. IEEE Computer Society, (2009)

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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture., , and . IEEE J. Solid State Circuits, 41 (12): 2650-2657 (2006)Test Generation for Weak Resistive Bridges., , and . ATS, page 265-272. IEEE, (2006)Introducing Redundant Computations in a Behavior for Reducing BIST Resources., , and . DAC, page 548-553. ACM Press, (1998)Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out., , and . VTS, page 358-367. IEEE Computer Society, (2001)Test generation in VLSI circuits for crosstalk noise., , and . ITC, page 641-650. IEEE Computer Society, (1998)Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs., , and . ITC, page 809-818. IEEE Computer Society, (1997)LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation., and . ITC, page 85-94. IEEE Computer Society, (1999)Test generation for crosstalk-induced delay in integrated circuits., , and . ITC, page 191-200. IEEE Computer Society, (1999)Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning., and . VTS, page 1-6. IEEE Computer Society, (2013)Process variation oriented delay testing of SRAMs., and . VTS, page 1-6. IEEE Computer Society, (2016)