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A recurrent crossbar of memristive nanodevices implements online novelty detection.

C. Bennett, D. Querlioz, и J. Klein. ICRC, стр. 1-4. IEEE Computer Society, (2016)

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Jacques Klein

Jacques-Olivier Lachaud

Jerome Olivier Klein

Jacques Latta

Jacques Neumann

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Synthesis of Finite State Machines with Magnetic Domain Wall Logic.J. Klein, E. Belhaire, C. Chappert, F. Ouchet, R. Cowburn, D. Read, и D. Petit. ISCAS, стр. 133-136. IEEE, (2007)Spin-electronics based logic fabrics.W. Zhao, J. Klein, Z. Wang, Y. Zhang, N. Romdhane, D. Querlioz, D. Ravelosona, и C. Chappert. VLSI-SoC, стр. 174-179. IEEE, (2013)Magnetic Adder Based on Racetrack Memory.H. Trinh, W. Zhao, J. Klein, Y. Zhang, D. Ravelosona, и C. Chappert. IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (6): 1469-1477 (2013)Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.E. Deng, Y. Zhang, W. Kang, B. Dieny, J. Klein, G. Prenat, и W. Zhao. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (7): 1757-1765 (2015)Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.G. Wang, Y. Zhang, B. Zhang, B. Wu, J. Nan, X. Zhang, Z. Zhang, J. Klein, D. Ravelosona, Z. Wang и 2 other автор(ы). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 215-225 (2019)Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.W. Zhao, M. Moreau, E. Deng, Y. Zhang, J. Portal, J. Klein, M. Bocquet, H. Aziza, D. Deleruyelle, C. Muller и 4 other автор(ы). IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (2): 443-454 (2014)Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.Y. Zhang, C. Zhang, J. Klein, D. Ravelosona, G. Sun, и W. Zhao. ISCAS, стр. 381-384. IEEE, (2015)Synchronous full-adder based on complementary resistive switching memory cells.Y. Zhang, E. Deng, J. Klein, D. Querlioz, D. Ravelosona, C. Chappert, W. Zhao, M. Moreau, J. Portal, M. Bocquet и 3 other автор(ы). NEWCAS, стр. 1-4. IEEE, (2013)Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.T. Hirtzlin, B. Penkovsky, J. Klein, N. Locatelli, A. Vincent, M. Bocquet, J. Portal, и D. Querlioz. NANOARCH, стр. 1-5. IEEE, (2019)Embedded MRAM for high-speed computing.W. Zhao, Y. Zhang, Y. Lakys, J. Klein, D. Etiemble, D. Revelosona, C. Chappert, L. Torres, L. Cargnini, R. Brum и 2 other автор(ы). VLSI-SoC, стр. 37-42. IEEE, (2011)

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