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Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.

, , , , and . ASP-DAC, page 543-548. IEEE, (2017)

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Power minimization for dynamic PLAs., , , and . ASP-DAC, page 1010-1013. ACM Press, (2005)Clock skew optimization considering complicated power modes., , , and . DATE, page 1474-1479. IEEE Computer Society, (2010)Memory-efficient pattern matching architectures using perfect hashing on graphic processing units., , , and . INFOCOM, page 1978-1986. IEEE, (2012)Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions., , and . EDAC-ETC-EUROASIC, page 620-624. IEEE Computer Society, (1994)Multiple wire reconnections based on implication flow graph., and . ACM Trans. Design Autom. Electr. Syst., 11 (4): 939-952 (2006)Contactless Stacked-die Testing for Pre-bond Interposers., , , , and . DAC, page 8:1-8:6. ACM, (2014)Embedding Repeaters in Silicon IPs for Cross-IP Interconnections., , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 597-601 (2013)Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (9): 1330-1334 (2009)Charge-sharing alleviation and detection for CMOS domino circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (2): 266-280 (2001)A timing-driven pseudoexhaustive testing for VLSI circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (1): 147-158 (2001)