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16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation.

, , , , , , , and . ISSCC, page 254-256. IEEE, (2020)

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Automated synthesis of complex analog circuits., , , and . ECCTD, page 20-23. IEEE, (2007)A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC., , , , , and . ESSCIRC, page 207-210. IEEE, (2021)A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion., , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2360-2374 (2021)22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC., , , , , , , and . ISSCC, page 396-398. IEEE, (2024)Calibration Techniques for Optimizing Performance of High-Speed ADCs., , , and . CICC, page 1-8. IEEE, (2023)A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion., , , , , , and . ISSCC, page 58-60. IEEE, (2019)16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation., , , , , , , and . ISSCC, page 254-256. IEEE, (2020)A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers., , , , and . IEEE J. Solid State Circuits, 54 (3): 646-658 (2019)A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS., , , , and . ESSCIRC, page 389-392. IEEE, (2023)A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier., , , , , , , and . IEEE J. Solid State Circuits, 57 (6): 1673-1683 (2022)