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A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 44 (12): 3580-3589 (2009)A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (4): 978-985 (2005)Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications., , , , , , and . ASP-DAC, page 667-672. IEEE, (2020)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 45 (10): 2016-2029 (2010)A CMOS multichannel 10-Gb/s transceiver., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 38 (12): 2094-2100 (2003)Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine., , , , , , , , , and 1 other author(s). CISIS, volume 611 of Advances in Intelligent Systems and Computing, page 432-438. Springer, (2017)