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s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.

K. Kanda, H. Tamura, T. Yamamoto, S. Matsubara, M. Kibune, Y. Doi, T. Shibasaki, N. Tzartzanis, A. Kristensson, S. Parikh, S. Ide, Y. Tsunoda, T. Yamabana, M. Sugawara, N. Kuwata, T. Ikeuchi, J. Ogawa, and W. Walker. IEEE J. Solid State Circuits, 44 (12): 3580-3589 (2009)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, S. Ohmoto, K. Tateishi, O. Tyshchenko, A. Sheikholeslami and 5 other author(s). ISSCC, page 168-169. IEEE, (2010)Optimizing effective interconnect capacitance for FPGA power reduction.S. Huda, J. Anderson, and H. Tamura. FPGA, page 11-20. ACM, (2014)Charge recycling for power reduction in FPGA interconnect.S. Huda, J. Anderson, and H. Tamura. FPL, page 1-8. IEEE, (2013)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.Y. Doi, S. Masaki, T. Chiba, H. Higashi, H. Yamaguchi, H. Takauchi, H. Ishida, K. Gotoh, J. Ogawa, and H. Tamura. CICC, page 131-134. IEEE, (2005)Jitter injection for on-chip jitter measurement in PI-based CDRs.J. Liang, A. Sheikholeslami, H. Tamura, and H. Yamaguchi. CICC, page 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.C. Ting, M. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura. CICC, page 1-4. IEEE, (2014)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.M. Jalali, R. Shivnaraine, A. Sheikholeslami, M. Kibune, and H. Tamura. CICC, page 1-8. IEEE, (2013)A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto, and T. Kuroda. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2456-2462 (2010)A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T. Cheung, J. Ogawa, N. Tzartzanis, W. Walker, and T. Kuroda. IEEE J. Solid State Circuits, 40 (8): 1680-1687 (2005)A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.Y. Tomita, H. Tamura, M. Kibune, J. Ogawa, K. Gotoh, and T. Kuroda. IEEE J. Solid State Circuits, 42 (3): 627-636 (2007)

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Disambiguation of "Tamura, Hirotaka"

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A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.

Please choose a person to relate this publication to

Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tamura, Hirotaka"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.

Please choose a person to relate this publication to

Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.