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Direct optimization of a PCI express link equalization in industrial post-silicon validation., , , and . LATS, page 1-6. IEEE, (2018)A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (2): 181-190 (2016)Thrill-K Architecture: Towards a Solution to the Problem of Knowledge Based Understanding., , , , , , and . AGI, volume 13539 of Lecture Notes in Computer Science, page 404-412. Springer, (2022)Fusing Temporal Graphs into Transformers for Time-Sensitive Question Answering., , , and . EMNLP (Findings), page 948-966. Association for Computational Linguistics, (2023)TempoQR: Temporal Question Reasoning over Knowledge Graphs., , , , , , , and . CoRR, (2021)Bug localization techniques for effective post-silicon validation., , , and . ASP-DAC, page 291. IEEE, (2012)Post-silicon validation challenges: how EDA and academia can help., , and . DAC, page 3-7. ACM, (2010)Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 733-740 (2019)Innovative practices session 1C: Post-silicon validation., and . VTS, page 1-2. IEEE Computer Society, (2013)TempoQR: Temporal Question Reasoning over Knowledge Graphs., , , , , , , and . AAAI, page 5825-5833. AAAI Press, (2022)