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3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication.

, , , , , , , and . J. Signal Process. Syst., 84 (3): 295-307 (2016)

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A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1173-1184 (2019)A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors., , , , , , , , , and 4 other author(s). ISSCC, page 316-318. IEEE, (2019)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , and . VLSI Circuits, page 65-66. IEEE, (2018)Welcome to ISQED 2013., , , , , , , and . ISQED, IEEE, (2013)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)Resilient microprocessor design for high performance & energy efficiency., , , , , , , , , and 1 other author(s). ISLPED, page 355-356. ACM, (2010)Resilient design in scaled CMOS for energy efficiency., , , , , , , , , and 2 other author(s). ASP-DAC, page 625. IEEE, (2010)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor., , , and . VLSI Circuits, page 1-2. IEEE, (2020)