( en | de | ru )

 

Disambiguation of "Bhat, Ritesh"

Author of the publication

copydeleteadd this publication to your clipboard
A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology.

, , , , , , , , , , , and . ISSCC, page 78-80. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ganapathi Bhat

Sooraj Bhat

Ritesh Rajani

Ritesh Gupta

Ritesh Shah

 

Other publications of authors with the same name

Wideband Mixed-Domain Multi-Tap Finite-Impulse Response Filtering of Out-of-Band Noise Floor in Watt-Class Digital Transmitters., , and . IEEE J. Solid State Circuits, 52 (12): 3405-3420 (2017)A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology., , , , , , , , , and 2 other author(s). ISSCC, page 78-80. IEEE, (2022)13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor., , and . ISSCC, page 234-235. IEEE, (2017)Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC Transmitters., and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1039-1043 (2016)A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 58 (12): 3364-3379 (December 2023)A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET., , , , , , , , , and 2 other author(s). ISSCC, page 284-285. IEEE, (2023)A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 57 (12): 3582-3598 (2022)