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Disambiguation of "Iakymchuk, Taras"

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A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks.

, , , , and . IEEE Access, (2019)

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Roman Iakymchuk

Taras Ptashnyk

Taras Chagala

Richard Taras

Taras Vynnyk

 

Other publications of authors with the same name

Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems., , , , , , , , and . ISCAS, page 1. IEEE, (2017)Hardware-efficient matrix inversion algorithm for complex adaptive systems., , , and . ICECS, page 41-44. IEEE, (2012)Fast spiking neural network architecture for low-cost FPGA devices., , , and . ReCoSoC, page 1-6. IEEE, (2012)Novel Resistance Measurement Method: Analysis of Accuracy and Thermal Dependence with Applications in Fiber Materials., , and . Sensors, 16 (12): 2129 (2016)Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices., , , , and . IEEE Trans. Computers, 65 (11): 3470-3479 (2016)An Event-based Fast Movement Detection Algorithm for a Positioning Robot Using POWERLINK Communication., , , and . CoRR, (2017)Simplified spiking neural network architecture and STDP learning algorithm applied to image classification., , , , and . EURASIP J. Image Video Process., (2015)Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise., , , and . ICECS, page 45-48. IEEE, (2012)An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links., , , , , , and . ISCAS, page 1556-1559. IEEE, (2014)On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems., , , , , , , , , and . IEEE Trans. Biomed. Circuits Syst., 11 (5): 1133-1147 (2017)