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A dynamic test compaction procedure for high-quality path delay testing.

M. Fukunaga, S. Kajihara, X. Wen, T. Maeda, S. Hamada, and Y. Sato. ASP-DAC, page 348-353. IEEE, (2006)

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Yasuo Kamata

Yasuo Tokunaga

Makoto Sato

Yasuo Nakayama

Nobuko Sato

Other publications of authors with the same name

Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip.S. Wang, Y. Sato, S. Kajihara, and H. Takahashi. J. Low Power Electron., 11 (4): 528-540 (2015)Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration.Y. Sato, I. Yamazaki, H. Yamanaka, T. Ikeda, M. Takakura, and K. Iwasaki. IEICE Trans. Inf. Syst., 87-D (9): 2179-2185 (2004)Connected word recognition by overlap and split of reference patterns and its performance evaluation tests.K. Tajima, M. Komura, and Y. Sato. ICASSP, page 1101-1104. IEEE, (1986)Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides.Y. Kohiyama, C. Ravikumar, Y. Sato, L. Wang, and Y. Zorian. ATS, page 207. IEEE, (2007)Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.X. Lin, K. Tsai, C. Wang, M. Kassab, J. Rajski, T. Kobayashi, R. Klingenberg, Y. Sato, S. Hamada, and T. Aikyo. ATS, page 139-146. IEEE, (2006)Invisible delay quality - SDQM model lights up what could not be seen.Y. Sato, S. Hamada, T. Maeda, A. Takatori, Y. Nozuyama, and S. Kajihara. ITC, page 9. IEEE Computer Society, (2005)Application of High-Quality Built-In Test to Industrial Designs.K. Hatayama, M. Nakao, Y. Kiyoshige, K. Natsume, Y. Sato, and T. Nagumo. ITC, page 1003-1012. IEEE Computer Society, (2002)Multi-cycle Test with Partial Observation on Scan-Based BIST Structure.Y. Sato, H. Yamaguchi, M. Matsuzono, and S. Kajihara. Asian Test Symposium, page 54-59. IEEE Computer Society, (2011)A Scan-Out Power Reduction Method for Multi-cycle BIST.S. Wang, Y. Sato, K. Miyase, and S. Kajihara. Asian Test Symposium, page 272-277. IEEE Computer Society, (2012)Genetic algorithm based approach for segmented testing.X. Fan, S. Reddy, S. Wang, S. Kajihara, and Y. Sato. DSN Workshops, page 85-90. IEEE Computer Society, (2011)

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Disambiguation of "Sato, Yasuo"

copy delete add this publication to your clipboard
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URL
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A dynamic test compaction procedure for high-quality path delay testing.

Please choose a person to relate this publication to

Yasuo Kamata

Yasuo Tokunaga

Makoto Sato

Yasuo Nakayama

Nobuko Sato

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sato, Yasuo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A dynamic test compaction procedure for high-quality path delay testing.

Please choose a person to relate this publication to

Yasuo Kamata

Yasuo Tokunaga

Makoto Sato

Yasuo Nakayama

Nobuko Sato

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A dynamic test compaction procedure for high-quality path delay testing.