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Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration., , , , , and . IEICE Trans. Inf. Syst., 87-D (9): 2179-2185 (2004)Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip., , , and . J. Low Power Electron., 11 (4): 528-540 (2015)Connected word recognition by overlap and split of reference patterns and its performance evaluation tests., , and . ICASSP, page 1101-1104. IEEE, (1986)Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides., , , , and . ATS, page 207. IEEE, (2007)Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects., , , , , , , , , and . ATS, page 139-146. IEEE, (2006)Invisible delay quality - SDQM model lights up what could not be seen., , , , , and . ITC, page 9. IEEE Computer Society, (2005)Application of High-Quality Built-In Test to Industrial Designs., , , , , and . ITC, page 1003-1012. IEEE Computer Society, (2002)Multi-cycle Test with Partial Observation on Scan-Based BIST Structure., , , and . Asian Test Symposium, page 54-59. IEEE Computer Society, (2011)A Scan-Out Power Reduction Method for Multi-cycle BIST., , , and . Asian Test Symposium, page 272-277. IEEE Computer Society, (2012)Genetic algorithm based approach for segmented testing., , , , and . DSN Workshops, page 85-90. IEEE Computer Society, (2011)