( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A dynamic test compaction procedure for high-quality path delay testing.

, , , , , и . ASP-DAC, стр. 348-353. IEEE, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Xiaoqing Pan

Xiaoqing Liu

Xiaoqing Li

Xiaoqing Shen

Xiaoqing Jin

 

Другие публикации лиц с тем же именем

Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test., , и . PRDC, стр. 124-129. IEEE, (2019)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , и . ITC-Asia, стр. 139-144. IEEE, (2019)Test Pattern Modification for Average IR-Drop Reduction., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 38-49 (2016)Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding., , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , и . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing., , , , и . IEICE Trans. Inf. Syst., 94-D (4): 833-840 (2011)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , и . IEEE Des. Test Comput., 25 (2): 122-130 (2008)Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications., , , , , , , и . ATS, стр. 43-48. IEEE, (2019)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , и 2 other автор(ы). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (3): 499-512 (2016)