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Disambiguation of "Waidyasooriya, Hasitha Muthumala"

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Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture.

, , and . IEICE Trans. Electron., 92-C (4): 539-549 (2009)

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Karunasiri Muthumala

 

Other publications of authors with the same name

Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability., and . IEEE Access, (2019)Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology., , , and . IEEE Trans. Parallel Distributed Syst., 28 (5): 1390-1402 (2017)Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems., , , and . SCFA, volume 10776 of Lecture Notes in Computer Science, page 146-155. Springer, (2018)A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA., , , , , , and . CANDAR Workshops, page 103-108. IEEE, (2019)OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions., , , and . Int. J. Reconfigurable Comput., (2017)Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2658-2669 (2015)Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (1): 342-351 (2011)