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Disambiguation of "Kameyama, Michitaka"

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Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture.

, , and . IEICE Trans. Electron., 92-C (4): 539-549 (2009)

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Michitaka Ota

Shin'ichi Kameyama

 

Other publications of authors with the same name

Interconnection-Free Biomolecular Computing., , and . Computer, 25 (11): 41-50 (1992)Low-power multiple-valued current-mode integrated circuit with current-source control and its application., , and . ASP-DAC, page 413-418. IEEE, (1997)An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture., , , and . ASP-DAC, page 89-90. IEEE, (2011)A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., and . APCCAS, page 1803-1806. IEEE, (2006)Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates., , , and . IEICE Trans. Electron., 95-C (8): 1434-1443 (2012)Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 619-630 (2015)Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects., , and . J. Robotics Mechatronics, 8 (6): 501-507 (1996)Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic., , and . J. Multiple Valued Log. Soft Comput., 11 (5-6): 619-632 (2005)Reversible, Information-Preserving Logic and Its Application., , , and . J. Multiple Valued Log. Soft Comput., 23 (3-4): 379-406 (2014)Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures., , , and . J. Multiple Valued Log. Soft Comput., 20 (5-6): 595-623 (2013)