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Disambiguation of "Gössel, Michael"

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Accelerated Shift Registers for X-tolerant Test Data Compaction.

, , , , and . ETS, page 133-139. IEEE Computer Society, (2008)

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Michael Gössel

Michael Gössel

Bernd Gössel

Ingrid Gössel

Ulrike Gössel

 

Other publications of authors with the same name

Memories for Parallel Subtree-Access., and . Parallel Algorithms and Architectures, volume 269 of Lecture Notes in Computer Science, page 122-130. Springer, (1987)Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten II., and . Elektronische Informationsverarbeitung und Kybernetik, 9 (9): 549-567 (1973)Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten I., and . Elektronische Informationsverarbeitung und Kybernetik, 9 (7/8): 433-454 (1973)Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors., , and . IOLTS, page 116-121. IEEE, (2014)Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs., and . J. Electron. Test., 4 (3): 267-281 (1993)On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture., , , , , and . ETS, page 239-246. IEEE Computer Society, (2006)Self-checking Carry-selectAdder with Sum-bit Duplication., , , and . ARCS Workshops, volume P-41 of LNI, page 84-91. GI, (2004)Parallel matrix multiplication on an array-logical processor., , , and . Recent Issues in Pattern Analysis and Recognition, volume 399 of Lecture Notes in Computer Science, page 72-78. Springer, (1989)Test set enrichment using a probabilistic fault model and the theory of output deviations., , and . DATE, page 1270-1275. European Design and Automation Association, Leuven, Belgium, (2006)Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design., and . VTS, page 151-157. IEEE Computer Society, (1994)