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Accelerated Shift Registers for X-tolerant Test Data Compaction.

, , , , и . ETS, стр. 133-139. IEEE Computer Society, (2008)

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Michael Gössel

Michael Gössel

Bernd Gössel

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Ulrike Gössel

 

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Memories for Parallel Subtree-Access., и . Parallel Algorithms and Architectures, том 269 из Lecture Notes in Computer Science, стр. 122-130. Springer, (1987)Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors., , и . IOLTS, стр. 116-121. IEEE, (2014)Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten II., и . Elektronische Informationsverarbeitung und Kybernetik, 9 (9): 549-567 (1973)Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten I., и . Elektronische Informationsverarbeitung und Kybernetik, 9 (7/8): 433-454 (1973)Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs., и . J. Electron. Test., 4 (3): 267-281 (1993)Self-checking Carry-selectAdder with Sum-bit Duplication., , , и . ARCS Workshops, том P-41 из LNI, стр. 84-91. GI, (2004)Parallel matrix multiplication on an array-logical processor., , , и . Recent Issues in Pattern Analysis and Recognition, том 399 из Lecture Notes in Computer Science, стр. 72-78. Springer, (1989)Test set enrichment using a probabilistic fault model and the theory of output deviations., , и . DATE, стр. 1270-1275. European Design and Automation Association, Leuven, Belgium, (2006)Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design., и . VTS, стр. 151-157. IEEE Computer Society, (1994)New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability., , и . IOLTS, стр. 37-42. IEEE Computer Society, (2008)