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Disambiguation of "Hanyu, Takahiro"

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Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.

, , , , , , , , , , , , , and . ISSCC, page 194-195. IEEE, (2013)

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Takahiro Kato

Hanyu Ye

Takahiro Moriyama

Takahiro Kirihara

Takahiro Nishiyama

 

Other publications of authors with the same name

NoC-MRAM architecture for memory-based computing: Database-search case study., , , , , , , and . NEWCAS, page 309-312. IEEE, (2017)Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link., , , and . APCCAS, page 683-686. IEEE, (2014)Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system., , , and . ISCAS, page 2067-2070. IEEE, (2011)Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit., , , , , , , , and . IEICE Trans. Electron., 93-C (5): 602-607 (2010)Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing., and . IEICE Trans. Electron., 89-C (11): 1598-1604 (2006)Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation., and . IEICE Trans. Electron., 91-C (4): 589-594 (2008)Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device., and . IEICE Trans. Electron., 94-C (8): 1302-1310 (2011)Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic., and . IEICE Trans. Electron., 89-C (11): 1575-1580 (2006)Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme., , , and . IEICE Trans. Inf. Syst., 93-D (8): 2080-2088 (2010)Efficient CMOS Invertible Logic Using Stochastic Computing., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (6): 2263-2274 (2019)