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Static analysis for fast and accurate design space exploration of caches.

, and . CODES+ISSS, page 103-108. ACM, (2008)

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Modeling out-of-order processors for WCET analysis., , and . Real Time Syst., 34 (3): 195-227 (2006)Modeling Control Speculation for Timing Analysis., , and . Real Time Syst., 29 (1): 27-58 (2005)An efficient framework for dynamic reconfiguration of instruction-set customization., , and . Des. Autom. Embed. Syst., 13 (1-2): 91-113 (2009)Application-Specific Processors.. Handbook of Hardware/Software Codesign, (2017)Guest Editors' Introduction: Special Issue on Time-Critical Systems Design Part II., , and . IEEE Des. Test, 35 (4): 5-6 (2018)Analyzing Loop Paths for Execution Time Estimation., , and . ICDCIT, volume 3816 of Lecture Notes in Computer Science, page 458-469. Springer, (2005)KLEESPECTRE: Detecting Information Leakage through Speculative Cache Attacks via Symbolic Execution., , , , and . CoRR, (2019)Instruction-set customization for real-time embedded systems., and . DATE, page 1472-1477. EDA Consortium, San Jose, CA, USA, (2007)Design Space exploration of FPGA-based accelerators with multi-level parallelism., , , , , and . DATE, page 1141-1146. IEEE, (2017)A Framework to Model Branch Prediction for WCET Analysis, and . (June 2002)Short version of: A Framework to Model Branch Prediction for WCET Analysis, Tulika Mitra, Abhik Roychoudhury, 2nd Workshop on Worst Case Execution Time Analysis (WCET), Austria, June 2002. Also available as NUS Technical Report 11-01. One of Author's homepage: http://www.comp.nus.edu.sg/~abhik/.