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Disambiguation of "S, Ramprasath"

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3SAT on an All-to-All-Connected CMOS Ising Solver Chip.

, , , , , , , , and . CoRR, (2023)

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S Danischewski

S Hilt

S Ulrich

S Bachmann

S Hüttelmaier

 

Other publications of authors with the same name

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps., , , , , , , and . ISPD, page 159-166. ACM, (2022)A Skew-Normal Canonical Model for Statistical Static Timing Analysis., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2359-2368 (2016)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement., , , , , , and . DATE, page 148-153. IEEE, (2022)COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization., , , , , , , , , and 3 other author(s). (January 2024)Statistical Criticality Computation Using the Circuit Delay., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (5): 717-727 (2014)An efficient algorithm for statistical timing yield optimization., and . DAC, page 166:1-166:6. ACM, (2015)3SAT on an All-to-All-Connected CMOS Ising Solver Chip., , , , , , , , and . CoRR, (2023)Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology., , , , , , and . ESSDERC, page 69-72. IEEE, (2023)On the computation of criticality in statistical timing analysis., and . ICCAD, page 172-179. ACM, (2012)A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 4844-4857 (December 2023)