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Leveraging reconfigurability to raise productivity in FPGA functional debug., , , , and . DATE, page 292-295. IEEE, (2012)Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy., , and . DATE, page 1550-1555. IEEE, (2016)Compact Area and Performance Modelling for CGRA Architecture Evaluation., and . FPT, page 126-133. IEEE, (2018)Bitwidth-optimized hardware accelerators with software fallback., and . FPT, page 136-143. IEEE, (2013)The VTR project: architecture and CAD for FPGAs from verilog to routing., , , , , , , , and . FPGA, page 77-86. ACM, (2012)High-Level Synthesis of FPGA Circuits with Multiple Clock Domains., and . FCCM, page 109-116. IEEE Computer Society, (2018)Subleq⊝: An Area-Efficient Two-Instruction-Set Computer., , , and . IEEE Embed. Syst. Lett., 9 (2): 33-36 (2017)Streaming Accuracy: Characterizing Early Termination in Stochastic Computing., , and . ASP-DAC, page 320-325. IEEE, (2022)Clock power reduction for virtex-5 FPGAs., , and . FPGA, page 13-22. ACM, (2009)Impact of FPGA architecture on resource sharing in high-level synthesis., , , , , , and . FPGA, page 111-114. ACM, (2012)