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Disambiguation of "Mauro, Alfio Di"

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Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.

, , , , , , , , and . CoRR, (2023)

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Alexandra Di Mauro

Alfio Borzi

Christian Mauro

Alfio Marazzi

Alfio Pappalardo

 

Other publications of authors with the same name

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2450-2463 (2023)Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine., , , , , , , , , and 2 other author(s). CoRR, (2023)Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). CoRR, (2021)SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions., , , , , and . DATE, page 825-830. IEEE, (2022)TCN-CUTIE: A 1036 TOp/s/W, 2.72 uJ/Inference, 12.2 mW All-Digital Ternary Accelerator in 22 nm FDX Technology., , , , and . CoRR, (2022)TCN-CUTIE: A 1, 036-TOp/s/W, 2.72-µJ/Inference, 12.2-mW All-Digital Ternary Accelerator in 22-nm FDX Technology., , , , and . IEEE Micro, 43 (1): 42-48 (2023)4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). ISSCC, page 60-62. IEEE, (2021)A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications., , , , and . COOL CHIPS, page 1-3. IEEE, (2022)Embedded neuromorphic attention model leveraging a novel low-power heterogeneous platform., , , , , and . AICAS, page 1-5. IEEE, (2023)Live Demonstration: Exploiting Body-Biasing for Static Corner Trimming and Maximum Energy Efficiency Operation in 22nm FDX Technology., , , , and . ISCAS, page 1. IEEE, (2020)