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Disambiguation of "Ottavi, Gianmarco"

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Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.

, , , , , , , , and . CoRR, (2023)

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Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2450-2463 (2023)A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference., , , , , and . CoRR, (2020)A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics., , , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (5): 1038-1053 (2022)A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing., , , , , , , , , and 7 other author(s). ISSCC, page 326-327. IEEE, (2023)Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing., , , , , , , , , and . IEEE J. Solid State Circuits, 59 (1): 128-142 (January 2024)A transprecision floating-point cluster for efficient near-sensor data analytics., , , , , , , and . CoRR, (2020)Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , and . CoRR, (2022)A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks., , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 422-435 (2022)Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing., , , , , , , , and . CoRR, (2023)Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU., , , and . DSD, page 429-435. IEEE, (2023)