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Disambiguation of "Miremadi, Seyed Ghassem"

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Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.

, , , and . DSN, page 276-285. IEEE Computer Society, (2007)

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Schahin Seyed-Mahdavi Ruiz

Abdolhossein Miremadi

Sajed Miremadi

Ghassem Khoramnia

Ghassem Ghesmati

 

Other publications of authors with the same name

Directed Flooding: A Fault-Tolerant Routing Protocol for Wireless Sensor Networks., , and . Systems Communications, page 395-399. IEEE Computer Society, (2005)Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches., , , and . IEEE Trans. Computers, 65 (12): 3661-3675 (2016)QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs., , , , and . ISLPED, page 1-6. IEEE, (2017)Speedup analysis in simulation-emulation co-operation., , and . FPT, page 394-398. IEEE, (2002)Reducing Power Consumption in NoC Design with no Effect on Performance and Reliability., , and . ICECS, page 886-889. IEEE, (2007)Complement routing: A methodology to design reliable routing algorithm for Network on Chips., and . Microprocess. Microsystems, 34 (6): 163-173 (2010)Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors., , , and . Microelectron. Reliab., 51 (12): 2374-2387 (2011)RAW-Tag: Replicating in Altered Cache Ways for Correcting Multiple-Bit Errors in Tag Array., , , and . IEEE Trans. Dependable Secur. Comput., 16 (4): 651-664 (2019)LEXACT: Low Energy N-Modular Redundancy Using Approximate Computing for Real-Time Multicore Processors., and . IEEE Trans. Emerg. Top. Comput., 8 (2): 431-441 (2020)AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches., , , and . IEEE Trans. Emerg. Top. Comput., 7 (3): 481-492 (2019)