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Disambiguation of "Nakata, Shunji"

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Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 686-690 (2014)

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Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit., , , , , , , and . ISCAS, page 2474-2477. IEEE, (2010)Stability of adiabatic reversible charging using 1D-capacitor array between the power supply and ground.. IEICE Electron. Express, 4 (1): 9-14 (2007)General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (10): 2301-2314 (2012)Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage.. IEICE Electron. Express, 3 (13): 304-309 (2006)Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation., , , , and . IEICE Electron. Express, 7 (9): 640-646 (2010)Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current., , , , and . MWSCAS, page 1068-1071. IEEE, (2012)Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 2194-2203 (2014)Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield., , , , , , , and . IET Circuits Devices Syst., 6 (4): 260-270 (2012)Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 230-234 (2011)Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 686-690 (2014)