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Disambiguation of "Saint-Laurent, Martin"

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10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications.

, , , , , , , , , , , , and . ISSCC, page 176-177. IEEE, (2014)

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Laurent Martin

Tony Saint-Lôt

Curt Saint-George

Ulrich Saint-Paul

Amélie Saint André- Arnim

 

Other publications of authors with the same name

A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology., and . ISLPED, page 159-164. ACM, (2010)A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (5): 834-844 (2007)Energy efficient design techniques for a digital signal processor., and . ICICDT, page 1-4. IEEE, (2012)On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs., , and . ICCD, page 214-220. IEEE Computer Society, (2001)Power-aware multi-voltage custom memory models for enhancing RTL and low power verification., , and . ICCD, page 24-31. IEEE Computer Society, (2015)Cache Design for Low Power and High Yield., , , and . ISQED, page 103-107. IEEE Computer Society, (2008)A 65-nm pulsed latch with a single clocked transistor., , and . ISLPED, page 347-350. ACM, (2007)10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications., , , , , , , , , and 3 other author(s). ISSCC, page 176-177. IEEE, (2014)Optimal Sequencing Energy Allocation for CMOS Integrated Systems., , , and . ISQED, page 194-199. IEEE Computer Society, (2002)A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (1): 81-91 (2015)