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Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.

, , , , , , and . Des. Autom. Embed. Syst., 10 (2-3): 105-125 (2005)

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ROAD: Improving Reliability of Multi-core System via Asymmetric Aging., , and . ICCAD, page 1-8. ACM, (2019)Leakage and Aging Optimization Using Transmission Gate-Based Technique., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (1): 87-99 (2013)Rescuing RRAM-Based Computing From Static and Dynamic Faults., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2049-2062 (2021)CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials., , , , , , , , , and 5 other author(s). CoRR, (2023)An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation., , , and . Integr., (2021)A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation., , and . IEEE Access, (2022)BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (10): 1591-1595 (2014)ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (3): 357-369 (2017)Reducing aging on scratchpad memory using temporal- and FSM-based power management., , and . VLSI-DAT, page 1-4. IEEE, (2017)Analyzing the BTI Effect on Multi-bit Retention Registers., , , and . ICS, volume 274 of Frontiers in Artificial Intelligence and Applications, page 269-278. IOS Press, (2014)