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Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.

, , , , and . DATE, page 624-629. EDA Consortium, San Jose, CA, USA, (2007)

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Exploring circuit timing-aware language and compilation., , and . ASPLOS, page 345-356. ACM, (2011)Exploration of associative power management with instruction governed operation for ultra-low power design., , , and . DAC, page 152:1-152:6. ACM, (2016)Process variation characterization of chip-level multiprocessors., , , , and . DAC, page 694-697. ACM, (2009)Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging., , and . CODES+ISSS, page 235-244. ACM, (2012)Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems., , and . CODES+ISSS, page 105-110. ACM, (2007)Enabling Deep Voltage Scaling in Delay Sensitive L1 Caches., and . DSN, page 192-202. IEEE Computer Society, (2016)Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management., , and . DAC, page 48:1-48:6. ACM, (2017)Multi-optimization power management for chip multiprocessors., , , and . PACT, page 177-186. ACM, (2008)Compiler-guided instruction-level clock scheduling for timing speculative processors., , , , and . DAC, page 40:1-40:6. ACM, (2018)Efficient parameter variation sampling for architecture simulations., , , and . DATE, page 1578-1583. IEEE, (2011)