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Disambiguation of "Zeinolabedin, Seyed Mohammad Ali"

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A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI.

, , , , , , , and . NEWCAS, page 1-5. IEEE, (2023)

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Seyed Mohammad Ali Emrani

Seyed Mohammad Seyed Makki

Mohammad Ali

Mohammad Ali

Seyed Mohammad Faradjli

 

Other publications of authors with the same name

A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (10): 1690-1700 (2016)Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression., , , and . BioCAS, page 1-4. IEEE, (2021)Structuring of Contourlet Transform for Pipeline-Based Implementation., , , and . Circuits Syst. Signal Process., 35 (3): 953-976 (2016)An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 739-743 (2022)Real-time Hardware Implementation of ARM CoreSight Trace Decoder., , and . IEEE Des. Test, 38 (1): 69-77 (2021)Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator., , and . DATE, page 1606-1609. IEEE, (2021)An area- and power-efficient FIFO with error-reduced data compression for image/video processing., , , and . ISCAS, page 2277-2280. IEEE, (2014)An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (11): 2408-2416 (2015)A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI., , , , , , , and . NEWCAS, page 1-5. IEEE, (2023)Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS., , , , and . APCCAS, page 734-735. IEEE, (2016)