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Exploiting path delay test generation to develop better TDF tests for small delay defects., , , and . ITC, page 1-10. IEEE, (2017)Special session: Hot topics: Statistical test methods., , , , , and . VTS, page 1-2. IEEE Computer Society, (2015)Test application time minimization for RAS using basis optimization of column decoder., , , , and . ISCAS, page 2614-2617. IEEE, (2010)Sizing CMOS Circuits for Increased Transient Error Tolerance., , , and . IOLTS, page 11-16. IEEE Computer Society, (2004)Special session 4B: Elevator talks., , , , , , , , and . VTS, page 1. IEEE Computer Society, (2013)Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study., , and . ITC, page 362-369. IEEE Computer Society, (1997)An efficient channel routing algorithm for defective arrays., and . ICCAD, page 432-435. IEEE Computer Society, (1989)Scan based two-pattern tests: should they target opens instead of TDFs?. LATS, page 1-2. IEEE Computer Society, (2015)Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing., and . VLSI Design, page 763-768. IEEE Computer Society, (2007)A random access scans architecture to reduce hardware overhead., , and . ITC, page 9. IEEE Computer Society, (2005)