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Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.

, , , , and . IEEE Symposium on Computer Arithmetic, page 272-279. IEEE Computer Society, (2003)

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Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation., , and . ISLPED, page 56-59. ACM, (2001)Energy minimization method for optimal energy-delay extraction., , and . ESSCIRC, page 177-180. IEEE, (2003)Energy Optimization of High-Performance Circuits., , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 399-408. Springer, (2003)Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders., , , , and . IEEE Symposium on Computer Arithmetic, page 272-279. IEEE Computer Society, (2003)Architectural Considerations for Energy Efficiency., , and . ICCD, page 13-16. IEEE Computer Society, (2005)Performance Comparison of VLSI Adders Using Logical Effort., and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 25-34. Springer, (2002)