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Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.

, , , , и . IEEE Symposium on Computer Arithmetic, стр. 272-279. IEEE Computer Society, (2003)

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Vojin ivojnovi

Krunoslav Vojinovi

Vojin Smodlaka

Vojin Drenovac

Giuseppe G G Manzardo

 

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Partitioned Branch Condition Resolution Logic., , и . SBCCI, стр. 35-40. IEEE Computer Society, (2000)Some optimal schemes for ALU implementation in VLSI technology., и . IEEE Symposium on Computer Arithmetic, стр. 2-8. IEEE, (1985)Issues in CPU-coprocessor communication and synchronization.. Microprocess. Microprogramming, 24 (1-5): 695-700 (1988)Low-Power Soft Error Hardened Latch., и . PATMOS, том 5953 из Lecture Notes in Computer Science, стр. 256-265. Springer, (2009)Future directions in clocking multi-ghz systems., и . ISLPED, стр. 219. ACM, (2002)Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation., , и . ISLPED, стр. 56-59. ACM, (2001)Conditional pre-charge techniques for power-efficient dual-edge clocking., , и . ISLPED, стр. 56-59. ACM, (2002)A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers., , , и . PATMOS, том 3728 из Lecture Notes in Computer Science, стр. 724-732. Springer, (2005)An integrated multiplier for complex numbers., , и . VLSI Signal Processing, 7 (3): 213-222 (1994)Timing Characterization of Dual-edge Triggered Flip-flops., , и . ICCD, стр. 538-541. IEEE Computer Society, (2001)