( en | de | ru )

 

Disambiguation of "Lee, Jeong-A"

Author of the publication

copydeleteadd this publication to your clipboard
Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs.

, , , , and . PCM (1), volume 3767 of Lecture Notes in Computer Science, page 500-511. Springer, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jeong-Hoon Lee

Yoo-Jeong Lee

Jeong-Hoon Lee

Jeong-Keun Lee

Eun-Jeong Lee

 

Other publications of authors with the same name

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (6): 1298-1307 (2019)Ice Detection on Edge Device Based on Most Significant Digit First SVM., , , and . ICVIP, page 61-66. ACM, (2022)Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product., , , , , and . J. Signal Process. Syst., 95 (7): 815-829 (July 2023)Operation Net System: A Formal Design Representation Model for High-Level Synthesis of Asynchronous Systems Based on Transformations., , and . ICATPN, volume 3099 of Lecture Notes in Computer Science, page 435-453. Springer, (2004)Bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architectures using Particle Swarm Optimization., and . Microprocess. Microsystems, (2017)A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip., and . Microprocess. Microsystems, 38 (5): 375-398 (2014)Constant-Factor Redundant CORDIC for Angle Calculation and Rotation., and . IEEE Trans. Computers, 41 (8): 1016-1025 (1992)Discrete Fourier transform processors using CORDIC., and . Great Lakes Symposium on VLSI, page 260-265. IEEE, (1991)A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only)., and . FPGA, page 270. ACM, (2013)Adder with Reduced Latency and Minimized Interconnect for Streaming Inner Products., , , and . ACSCC, page 938-942. IEEE, (2021)