( en | de | ru )

 

Disambiguation of "Ramachandran, Champaka"

Author of the publication

copydeleteadd this publication to your clipboard
A performance driven logic synthesis system using delay estimator.

, , , , and . Great Lakes Symposium on VLSI, page 88-92. IEEE, (1994)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Harshawardhan Ramachandran

Muthupandi Ramachandran

Sheetal Ramachandran

Vimal Ramachandran

Haribaskar Ramachandran

 

Other publications of authors with the same name

Combined topological and functionality based delay estimation using a layout-driven approach for high level applications., and . EURO-DAC, page 72-78. IEEE Computer Society Press, (1992)An Empirical Study on the Effects of Physical Design in High-Level Synthesis., , , and . VLSI Design, page 11-16. IEEE Computer Society, (1994)Incorporating the Controller Effects During Register Transfer Level Synthesis., and . EDAC-ETC-EUROASIC, page 308-313. IEEE Computer Society, (1994)On the intrinsic Rent parameter and spectra-based partitioning methodologies., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (1): 27-37 (1994)A performance driven logic synthesis system using delay estimator., , , , and . Great Lakes Symposium on VLSI, page 88-92. IEEE, (1994)Accurate layout area and delay modeling for system level design., , , , and . ICCAD, page 355-361. IEEE Computer Society / ACM, (1992)On the intrinsic rent parameter and spectra-based partitioning methodologies., , , and . EURO-DAC, page 202-208. IEEE Computer Society Press, (1992)Evaluating layout area tradeoffs for high level applications., and . IEEE Trans. Very Large Scale Integr. Syst., 1 (1): 46-55 (1993)LAST: a Layout Area and Shape function esTimator for high level applications., and . EURO-DAC, page 351-355. EEE Computer Society, (1991)Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (12): 1450-1460 (1994)