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Optimized Built-In Self-Repair for Multiple Memories.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2174-2183 (2016)

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A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (5): 786-797 (2014)A New 3-D Fuse Architecture to Improve Yield of 3-D Memories., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (10): 1763-1767 (2016)A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories., , , and . Asian Test Symposium, page 301-306. IEEE Computer Society, (2013)Low power scan bypass technique with test data reduction., , , , and . ISQED, page 173-176. IEEE, (2015)A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (11): 2336-2349 (2014)A Survey of Repair Analysis Algorithms for Memories., , , , and . ACM Comput. Surv., 49 (3): 47:1-47:41 (2016)A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories., , , and . IEEE Trans. Reliability, 64 (2): 586-595 (2015)EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (7): 1130-1135 (2010)Optimized Built-In Self-Repair for Multiple Memories., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2174-2183 (2016)Fail Memory Configuration Set for RA Estimation., , , , , and . ITC, page 1-9. IEEE, (2020)