( en | de | ru )

 

Disambiguation of "Rose, Jonathan"

Author of the publication

copydeleteadd this publication to your clipboard
Timing-driven placement for FPGAs.

, , and . FPGA, page 203-213. ACM, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jonathan Burmeister

Jonathan Roericht

Jonathan Rother

Jonathan Vöglein

Jonathan Dörr

 

Other publications of authors with the same name

Speed and area tradeoffs in cluster-based FPGA architectures., , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (1): 84-93 (2000)A novel and efficient routing architecture for multi-FPGA systems., and . IEEE Trans. Very Large Scale Integr. Syst., 8 (1): 30-39 (2000)Fine-Grained Interconnect Synthesis., , and . ACM Trans. Reconfigurable Technol. Syst., 9 (4): 31:1-31:22 (2016)A detailed router for field-programmable gate arrays., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (5): 620-628 (1992)A stochastic model to predict the routability of field-programmable gate arrays., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (12): 1827-1838 (1993)Exploration and Customization of FPGA-Based Soft Processors., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (2): 266-277 (2007)A parameterized automatic cache generator for FPGAs., and . FPT, page 324-327. IEEE, (2003)Automatic FPGA system and interconnect construction with multicast and customizable topology., and . FPT, page 72-79. IEEE, (2015)Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters., and . FPT, page 57-64. IEEE, (2007)Measuring the gap between FPGAs and ASICs., and . FPGA, page 21-30. ACM, (2006)