Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA.

H. Fan, S. Liu, M. Ferianc, H. Ng, Z. Que, S. Liu, X. Niu, and W. Luk. FPT, page 14-21. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Zhiqiang Li

Zhang Que

Zhiqiang Wang

Zhiqiang Zhang

Zhiqiang Du

Other publications of authors with the same name

Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs.Z. Que, H. Nakahara, E. Nurvitadhi, A. Boutros, H. Fan, C. Zeng, J. Meng, K. Tsoi, X. Niu, and W. Luk. IEEE Trans. Very Large Scale Integr. Syst., 30 (2): 227-237 (2022)FPGA-Based Acceleration for Bayesian Convolutional Neural Networks.H. Fan, M. Ferianc, Z. Que, S. Liu, X. Niu, M. Rodrigues, and W. Luk. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5343-5356 (2022)In-circuit tuning of deep learning designs.Z. Que, D. Noronha, R. Zhao, X. Niu, S. Wilton, and W. Luk. J. Syst. Archit., (2021)Customizable FPGA-based Accelerator for Binarized Graph Neural Networks.Z. Wang, Z. Que, W. Luk, and H. Fan. ISCAS, page 1968-1972. IEEE, (2022)F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition.H. Fan, C. Luo, C. Zeng, M. Ferianc, Z. Que, S. Liu, X. Niu, and W. Luk. ASAP, page 1-8. IEEE, (2019)Applications and Techniques for Fast Machine Learning in Science.A. Deiana, N. Tran, J. Agar, M. Blott, G. Guglielmo, J. Duarte, P. Harris, S. Hauck, M. Liu, M. Neubauer and 77 other author(s). CoRR, (2021)Optimizing Reconfigurable Recurrent Neural Networks.Z. Que, H. Nakahara, E. Nurvitadhi, H. Fan, C. Zeng, J. Meng, X. Niu, and W. Luk. FCCM, page 10-18. IEEE, (2020)Sets are all you need: Ultrafast jet classification on FPGAs for HL-LHC.P. Odagiu, Z. Que, J. Duarte, J. Haller, G. Kasieczka, A. Lobanov, V. Loncar, W. Luk, J. Ngadiuba, M. Pierini and 6 other author(s). CoRR, (2024)Memory-Efficient Architecture for Accelerating Generative Networks on FPGA.S. Liu, C. Zeng, H. Fan, H. Ng, J. Meng, Z. Que, X. Niu, and W. Luk. FPT, page 30-37. IEEE, (2018)An Overlay for Rapid FPGA Debug of Machine Learning Applications.D. Noronha, R. Zhao, Z. Que, J. Goeders, W. Luk, and S. Wilton. FPT, page 135-143. IEEE, (2019)

BibSonomy

Disambiguation of "Que, Zhiqiang"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA.

Please choose a person to relate this publication to

Zhiqiang Li

Zhang Que

Zhiqiang Wang

Zhiqiang Zhang

Zhiqiang Du

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Que, Zhiqiang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA.

Please choose a person to relate this publication to

Zhiqiang Li

Zhang Que

Zhiqiang Wang

Zhiqiang Zhang

Zhiqiang Du

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA.