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Disambiguation of "Choi, Jung-Hwan"

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Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).

, , , , , , , , , , , , , , , , , , and . A-SSCC, page 169-172. IEEE, (2016)

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Sung-Hwan Choi

Hwan-Ok Jung

Jung-Hwan Kim

Seung Hwan Jung

Jung-Hwan Oh

 

Other publications of authors with the same name

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface., , , , , , , , , and 6 other author(s). VLSIC, page 182-. IEEE, (2015)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution., , , , , , , , , and 11 other author(s). ISSCC, page 316-317. IEEE, (2016)A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os., , , , and . IEEE J. Solid State Circuits, 58 (10): 2790-2800 (October 2023)A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface., , , , , , , , and . IEEE J. Solid State Circuits, 53 (1): 144-154 (2018)Mutual Interference Suppression and Signal Restoration in Automotive FMCW Radar Systems., , , , and . IEICE Trans. Commun., 102-B (6): 1198-1208 (2019)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration., , , , , , , , , and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)A Spatial Correlation Model for Shadow Fading in Indoor Multipath Propagation., , , and . VTC Fall, page 1-6. IEEE, (2010)A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus., , , , , , , , , and 24 other author(s). ISSCC, page 446-448. IEEE, (2022)A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)