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A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.

Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara, K. Nii, H. Kawai, H. Kawaguchi, and M. Yoshimoto. ISQED, page 16-23. IEEE, (2014)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Takuya Soma

Takuya Suzuki

Tobias Sawada

Paul Akio Sawada

Other publications of authors with the same name

Session Initiation Protocol (SIP) Usage of the Offer/Answer Model.S. Okumura, T. Sawada, and P. Kyzivat. RFC, (August 2011)Semi-Supervised Learning Based De-Raining Method for UAV.T. Sawada, T. Katayama, T. Song, and T. Shimamoto. ICCE, page 1-5. IEEE, (2023)Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging.T. Wadatsumi, K. Kawai, R. Hasegawa, T. Miki, M. Nagata, K. Muramatsu, H. Hasegawa, T. Sawada, T. Fukushima, and H. Kondo. IRPS, page 14-1. IEEE, (2022)An insertion loss control method for supplementing cancellation effect deteriorated by echo path change in hands free telecommunication system.K. Fujii, M. Muneyasu, T. Sawada, T. Yoshioka, and M. Morimoto. APCCAS, page 439-442. IEEE, (2014)An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference.T. Sawada, K. Yoshikawa, H. Takata, K. Nii, and M. Nagata. IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2347-2351 (2015)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara and 4 other author(s). IEICE Trans. Electron., 97-C (4): 332-341 (2014)Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging.T. Wadatsumi, K. Kawai, R. Hasegawa, K. Muramatsu, H. Hasegawa, T. Sawada, T. Fukushima, H. Kondo, T. Miki, and M. Nagata. IEICE Trans. Electron., 106 (10): 556-564 (October 2023)Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation.T. Sawada, T. Toshikawa, K. Yoshikawa, H. Takata, K. Nii, and M. Nagata. IEICE Trans. Electron., 95-C (4): 586-593 (2012)Character input system based on EMG signals generated by eye blinks.Y. Maruyama, T. Sawada, and K. Moriya. ACIT, page 7:1-7:6. ACM, (2019)A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara and 4 other author(s). ISQED, page 16-23. IEEE, (2014)

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Disambiguation of "Sawada, Takuya"

Please choose a person to relate this publication to

Takuya Soma

Takuya Suzuki

Tobias Sawada

Paul Akio Sawada

Paul Akio Sawada

Other publications of authors with the same name

Disambiguation