From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , и . SoCC, стр. 143-147. IEEE, (2012)A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2., , , и . VLSI Circuits, стр. 248-. IEEE, (2019)28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique., , , , , , , , , и 1 other автор(ы). IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 575-584 (2014)A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry., , , , , , и . ISQED, стр. 438-441. IEEE, (2013)A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 488-617. IEEE, (2007)A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline., , , , , , , и . VLSIC, стр. 1-2. IEEE, (2014)A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 326-606. IEEE, (2007)12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM., , , и . VLSI Circuits, стр. 19-20. IEEE, (2018)Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation., , , , , , и . SoCC, стр. 519-524. IEEE, (2010)A dynamic body-biased SRAM with asymmetric halo implant MOSFETs., , , , , , и . ISLPED, стр. 285-290. IEEE/ACM, (2011)