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A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract).

, , , , , , , , и . FPGA, стр. 256. ACM, (1998)

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Srinivas Reddy Pallerla

Edamakanti Chandrakanth Reddy

Srinivas Jagarlamudi

Srinivas Yarlanki

Girish Srinivas

 

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