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Disambiguation of "Sano, Toru"

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Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.

, , , , , , , , , and . IEICE Trans. Electron., 97-C (4): 360-368 (2014)

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Toru Nomura

Toru Matsuyama

Kazuhiko Sano

Toru Kashima

Richard Heinrich Torunsky

 

Other publications of authors with the same name

A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications., , , , , , , , , and 7 other author(s). ISSCC, page 132-134. IEEE, (2019)Development of low power many-core SoC for multimedia applications., , , , , and . DATE, page 773-777. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 55 (1): 120-132 (2020)18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters., , , , , , , , , and . IEICE Trans. Electron., 97-C (4): 360-368 (2014)A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications., , , , , , , , , and . VLSIC, page 150-151. IEEE, (2012)On Estimation of Tangential Force in Railways Brake Systems by Fuzzy Inference., , , and . J. Adv. Comput. Intell. Intell. Informatics, 19 (5): 639-644 (2015)Instruction buffer mode for multi-context Dynamically Reconfigurable Processors., , , , and . FPL, page 215-220. IEEE, (2008)A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array., , , , , and . ERSA, page 283-286. CSREA Press, (2009)Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors., , and . ERSA, page 112-118. CSREA Press, (2009)